Integrated circuit (IC) memory devices conventionally include static random access memory (SRAM). Conventional SRAM is based on four-transistor memory cells (4T SRAM cells) or six-transistor memory cells (6T SRAM cells) that are compatible with conventional memory elements, such as complementary metal-oxide-semiconductor (CMOS) devices, operate at low voltage levels and perform at relatively high speeds. However, conventional SRAM consumes a large cell area that limits high-density design of SRAM.
In attempts to reduce the area of IC memory devices, high-density, low-voltage SRAM cells including four layers of alternating n- and p-type silicon material, often referred to as a “thin capacitively-coupled thyristor (TCCT)” have been fabricated. As used herein, the term “thyristor,” means and includes a bi-stable, three-terminal device that includes a four layer structure including a p-type anode region, an n-type base, a p-type base, and an n-type cathode region arranged in a p-n-p-n configuration. The thyristor may include two main terminals, an anode and a cathode, and the control terminal, often referred to as the “gate,” which may be attached to the p-type material nearest the cathode. Thyristor-based random access memory (T-RAM) cells demonstrate faster switching speeds and lower operating voltages in comparison to conventional SRAM cells.
A thyristor in a memory device may be turned on by biasing the gate so that a p-n-p-n channel conducts a current. Once the device is turned on, often referred to as “latched,” the thyristor does not require the gate to be biased to maintain the current conducted between the cathode and the anode. Instead, it will continue to conduct until a minimum holding current is no longer maintained between the anode and cathode, or until the voltage between the anode and the cathode is reversed. Accordingly, the thyristor may function as a switch or diode capable of being switched between an “on” state and an “off” state.
Referring to FIG. 1A, a conventional T-RAM cell 10 includes a vertical Referring to FIG. 1A, a conventional T-RAM cell 10 includes a vertical thyristor 12 with a vertical surrounding gate 14 as a bi-stable element and an access transistor 16 formed on a silicon substrate 11. The thyristor 12 includes an anode region 18, an n base region 20, a p base region 22 and a cathode region 24. The T-RAM cell 10 is accessed by two word lines, a first word line 26 used to control an access gate of the access transistor 16 and the gate 14, which functions as the second word line during write operations, and is used to control switching of the vertical thyristor 12. The vertical thyristor 12 is connected to a reference voltage 28. The gate 14 may improve the switching speed of the vertical thyristor 12. A bit line 30 connects the T-RAM cell 10 to a sense amplifier (not shown) for reading and writing data from and to the T-RAM cell 10. The T-RAM cell 10 exhibits a very low standby current in the range of 10 pA.
However, there are several drawbacks associated with the T-RAM cell 10, including limitations on scalability, control and integration. For example, the T-RAM cells 10 are limited by difficulties in controlling the dimensions of each thyristor 12 as well as reproducing the dimensions for each thyristor 12 in an array. Due to difficulties in scaling the vertical thyristor 12 and the gate 14, the T-RAM cells 10 are difficult to scale to areas of less than 8F2, where F is the minimal feature size. Moreover, forming the doped regions of the thyristor 12 is hindered by implanting processes, which may lead to undesirable dopant concentrations or distributions in the thyristor 12. In addition, T-RAM cells 10 must be fabricated separate from any other devices, such as logic devices, which require extra fabrication acts. Finally, connection of the T-RAM cells 10 by means of the word line 26 and the gate 14 may lead to serial (i.e., cell-to-cell) resistance and device failure.
Accordingly, what is needed in the art are thyristor-based memory cells for forming devices having improved scalability, density and integration capacity and methods for forming the same.